1. Field of the Invention
The present invention relates to high speed computer memories, such as caches, in which the requested data may be stored in two adjoining lines, thus requiring a split line access in order to access the data stored on the two lines.
2. Description of Related Art
Computer performance can be improved by reducing the average number of clock cycles necessary to perform memory accesses. In many processors, two or more cycles are required to access main memory. In order to reduce the average number of cycles to access memory, high speed memories can be utilized. One example of a high speed memory is a "cache". Caches improve performance by storing and supplying frequently used instructions and data in one or two clock cycles rather than the two or more cycles generally required for a memory access. Effective use of a cache can result in substantial performance improvements, which is why many microprocessors now include one or more caches in their architecture.
Caches are organized in "lines". A cache may include hundreds of cache lines, each line including a selected block of memory which may be many bytes in length. There are many types of caches. In a fully associative cache, data can be stored in any cache line, regardless of its address. In a set associative cache, the cache lines are organized into "sets". Each set is assigned to hold data that has common lower address bits (the set address), and the cache lines in a particular set can hold data only if the lower bits match the set address. Because the set address uses the lower bits (but usually not the lowest bits) of an address, a long block of data can be stored in a series of sets. This is advantageous because data is usually read or written sequentially from a large block of memory.
A split line access occurs when a data or instruction access crosses over a cache line boundary, which means that part of the desired data resides on one cache line, and the remainder resides on another, adjoining cache line. To access those two lines using a conventional technique, two addresses are generated and supplied to two decoders which decode the addresses, and the two decoded lines are used to select two input ports in the memory which supply two outputs. Therefore, two address decoders and two output ports would be required using this conventional technique to select two cache lines during a split line access. However, the second decoder and second port are expensive in terms of silicon space, and increase complexity of the circuit. Furthermore, the second decoder and second port are not used often because split line accesses occur infrequently. A second alternative to split line access uses only one decoder and one output port, but requires two separate, sequential access operations to access the two lines. This second approach would usually greatly impact performance during a split line access because the processor must now wait for two accesses to complete and be validated.
It would be an advantage to provide a method and apparatus with a single decoder and a single ported data array that could simultaneously access and select two lines during a split line access.